1. Field of the Invention
The present invention relates to a Phase-Locked Loop (PLL) and, in particular, to an All Digital PLL (ADPLL) and oscillation signal generation method thereof that is capable of generating a spur-free oscillation signal by improving the frequency resolution of the ADPLL.
2. Description of the Related Art
With the advance of silicon processing technologies, the gate length of Metal Oxide Semiconductor (MOS) transistor has become shorter and shorter, whereby the performance of an analog circuit is likely to be influenced by change in fabrication process, voltage, and temperature. PLL is one of representative analog circuitry systems, such that it should be designed in consideration of such factors. One approach to reduce the influence by the variation of those factors is to replace the analog circuit of the PLL with a digital circuit.
An All Digital PLL (ADPLL) is a digital system implemented with digital logics except for the Digitally Controlled Oscillator (DCO) for generating oscillation signals. The ADPLL is less sensitive to the changes of the fabrication process, voltage, and temperatures and can be implemented by combining digital circuits, thereby facilitating design freedom in comparison with the analog PLL.
FIG. 1 is a circuit diagram illustrating a conventional ADPLL.
As shown in FIG. 1, the ADPLL 100 includes a DCO 110, a main feedback circuit 120 for feeding back the output signal of the DCO 110, a phase detector 132 for detecting a phase difference between the output signal of a phase accumulator 131 and the feedback signal, and a digital loop filter 140 for filtering the detected phase difference.
In the meantime, the ADPLL is sensitive to the quantization noise caused by the system's resolution limit, whereas it is less influenced by the variation of process, voltage, temperature, and analog noise characteristics in comparison with the analog PLL. Typically, the quantization noise is generated at the phase detector 132 and DCO 110, and the least phase difference interval that the phase detector 132 can measure is restricted by an inverter delay of a time-to-digital converter 123. The quantization noise increases the phase noise of the output signal of the ADPLL and forms a periodic pattern to incur spurs.
The digital loop filter 140 of the conventional ADPLL 100 has two paths: one is a Proportional Path 142, and the other is an Integral Path 141. In order to secure the system stability, the scale factor (α) of the first path 142 should be greater than the scale factor (β) of the second path 141 and, otherwise, the ADPLL 100 may diverge. Among the quantization noises influencing to the performance of ADPLL 100, the quantization noise of the phase detector 132 propagates to the DCO 110 through the first and second paths 142 and 141. Since the scale factor (α) of the first path 142 is greater than the scale factor (β), the DCO 110 is influenced predominantly by the quantization noise propagated via the first path 142.
In the conventional ADPLL, it is required to increase a number of bits of the frequency command signal (N) in order to increase the frequency resolution. However, increase of the bit number of the frequency command signal (N) causes the increase of the entire system bit number, resulting in increase of system complexity.
Accordingly, there has been a need for an enhanced ADPLL that is capable of canceling spurs with improvement of frequency resolution without compromising system complexity.